The present invention generally relates to testing semiconductor integrated circuits, and more particularly to generating address translation stimuli for post-silicon functional validation.
Post-silicon functional validation may be one of the final steps in testing the functionality of a semiconductor integrated circuit. Validation of post-silicon platforms may be performed with an exerciser, which may be loaded onto a device under testing (DUT). An exerciser generates test cases (e.g., programs, stimuli), executes the test cases (e.g., on the DUT), and checks the results. The stimuli generation component (e.g., stimuli generator, stimuli generation engine) in an exerciser should be kept simple due to limited hardware resource.
Some complex DUT areas, however, require heavy computation to produce interesting events and coverage. For such areas, external off-line stimuli generators may be utilized. An example of a complex DUT area is an address translation facility in a memory management unit, which may consist of numerous microarchitecture details and may require a dedicated off-line stimuli generator that may be significantly more complex than stimuli generators used for other DUT areas. In addition, a post-silicon exerciser may restrict the address translation stimuli generator due to limited hardware resources, e.g., memory. As a result, the address translation stimuli generator may not produce the desired stimuli in a reliable, consistent manner.
Typically, an address translation stimuli generator may utilize a constrained-random constrain satisfaction problem (CSP) solving engine (solver). However, since the post-silicon test environment may have limited memory, a generic CSP solver faces significant difficulties in finding solutions as memory space for translation tables is also limited.